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rev. 1.1 march 2012 page 1 of 1 www.aosmd.com AOZ1253 3a ezbuck ? synchronous buck regulator general description the AOZ1253 is a high efficiency, low quiescent current and simple to use 3a synchronous buck regulator. this device operates from 4.5v to 26v input voltage range and provides up to 3a of continuous output current with an adjustable output voltage down to 0.6v. the AOZ1253 is offered in the exposed pad so-8 package which is rated over a -40c to +85c ambient temperature range. features ? 4.5v to 26v input voltage operation range ? high efficiency pfm mode light load performance ? synchronous rectification: 115m ? integrated high-side switch and 30m ? internal low-side switch ? integrated bootstrap diode ? external soft start control ? adjustable output voltage down to 0.6v ? 3a continuous output current ? fixed frequency of pwm 620khz operation ? tailored for small profile inductor and ceramic capacitors ? cycle-by-cycle current limit ? short-circuit protection ? thermal shutdown ? standard exposed pad so-8 package ? -40c to 150c operating junction temperature range applications ? high performance point-of-load dc/dc converters ? notebook/ultra mobile pcs/servers ? pcie graphics cards/set top boxes ? set top boxes ? dvd drives and hdd ? lcd-tv/displays typical application
AOZ1253 page 2 of 2 rev. 1.1 march 2012 www.aosmd.com ordering information part number temperature range package environmental AOZ1253pi -40c to +85c epad so-8 green aos green products use reduced levels of halogens, and are also rohs compliant. please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information. pin configuration epad so-8 (top view) pin description part number pin name pin function 1 pgnd power ground connection. 2 vin input voltage supply pin. when vin rise s above the uvlo threshold the device starts up. note : connect close decoupling capacitor from vin to pgnd to minimize input switching loop. 3 bst bootstrap connection for high-side nfet gate drive input. connect 10nf capacitor from bst to lx. 4 ss soft start input. connect a capacitor betw een ss to gnd for soft start time control. 5 comp external loop compensation input. 6 agnd signal ground input. 7 fb the feedback voltage input. it is used to determi ne the output voltage via a resistor divider between the output and agnd. 8 vdd internal ldo voltage output. connec t a 1f capacitor close to vdd to agnd. exposed pad lx output connection to inducto r. thermal connection for output stage. vin bst exposed pad lx 2 3 ss 4 pgnd 1 fb agnd 7 6 comp 5 vdd 8
AOZ1253 page 3 of 3 rev. 1.1 march 2012 www.aosmd.com functional block
AOZ1253 page 4 of 4 rev. 1.1 march 2012 www.aosmd.com absolute maximum ratings exceeding the absolute maximum ratings may damage the device. parameter rating supply voltage (v in ) 30v lx to gnd -0.7v to vin+0.3v ss to gnd -0.3v to +6v bst to lx -0.3v to +6v fb to gnd -0.3v to +6v comp to gnd -0.3v to +6v junction temperature (t j ) +150c storage temperature (t s ) -65c to +150c esd rating (1) 2kv note: 1. devices are inherently esd sens itive, handling precautions are required. human body model rating: 1.5k ? in series with 100pf. recommended operating ratings this device is not guaranteed to operate beyond the recommended operating ratings. parameter rating supply voltage (v in ) 4.5v to 26v output voltage (v out ) 0.6v to vin ambient temperature (t a ) -40c to +85c package thermal resistance epad so-8 ( ? electrical characteristics t a = 25c, v vin = 12v, v ss = 2.5v, v out = 3.3v unless otherwise specified. specifications in bold indicate an ambient temperature range of -40c to +85c. symbol parameter conditions min. typ. max units v vin supply voltage 4.5 26 v v uvlo input under-voltage lockout threshold v vin rising v vin falling 3.3 4.1 v i vin supply current (quiescent) i out = 0, vfb = 0.8v 0.9 1.5 ma i off shutdown supply current v ss = 0v 20 a v vdd ldo voltage v vin > 6v 5.2 v v fb feedback voltage 591 600 609 mv v fb_load load regulation 0.8a < i out < 3.2a 0.5 % v fb_line line regulation 6v < v vin < 26v, load = 1a 0.05 %/v i fb feedback input current v fb = 0.6v 100 na v ss_off enable threshold off threshold 0.4 v i ss ss source current v ss = 2.0v -30 2.5 30 a modulator f s frequency 500 620 740 khz d max maximum duty cycle 87 % t on_min minimum on time 80 ns gm sys system loop transconductance i out /v comp 5 a/v gm ea error amplifier transconductance 1 ma/v protection i lim current limit 4 4.5 a t otp_rise over-temperature shutdown limit temperature rising 155 c t otp_fall temperature falling 115 c outputs r dson_hs high-side switch on resistance 115 170 m ? r dson_hs low-side switch on resistance 30 60 m ?
AOZ1253 page 5 of 5 rev. 1.1 march 2012 www.aosmd.com typical performance characteristics t a = 25c, v in = 12v, v out = 1.1v unless other wise specified.
AOZ1253 page 6 of 6 rev. 1.1 march 2012 www.aosmd.com detailed description the AOZ1253 is a high efficiency current-mode buck regulator with integrated both high-side and low-side nmos switches. it has a wide operating input voltage range of 4.5v to 26v and can supply up to 3a of output load current. AOZ1253?s key protection features include input under voltage lockout, output over voltage protection, cycle by cycle current limit, fault short protection and thermal shut down. the AOZ1253 is available in the exposed pad so-8 package. soft start AOZ1253 starts a soft start that can be adjusted by an external capacitor. the internal 2.5a current source starts to charge the external capacitor through the soft- start pin. when soft-start voltage is higher than internal enable threshold voltage, the ic starts to switch with minimum on-time. with the soft-start voltage further increasing, the ic starts to switch with wider on-time, which drives the output (fb) following the soft-start voltage until output reaches the pre-set value. the output soft-start time can be calculated by: ss ss ss i c t ? ? 6 . 0 light load and pwm operation under low output current settings, AOZ1253 will operate in light load mode to obtain high efficiency. the two modes of operation, pfm and pwm are determined by the peak inductor current level and the output feedback voltage. for very low output current and consequently low peak inductor current, AOZ1253 will operate under critical inductor current mode if fb voltage is lower than threshold of v h_pfm . v h_pfm is 10mv higher than normal voltage reference. if output is higher than that value, ic will turn-off to keep high light load efficiency. as the output current increases, the ic will leave pfm mode and will enter pwm mode operating in fixed frequency continuous conduction mode (ccm). in ccm mode, AOZ1253 operates with the low side mosfet switching in synchronous rectification to obtain high efficiency performance. error amplifier AOZ1253 uses an error amplifier that has a transconductance of 1000a/v. closed loop stability is realized through the frequency compensation network connected between comp to agnd. (refer to loop compensation) slope compensation a slope compensation ramp is also added in the control loop design to prevent sub harmonic oscillations. there is sufficient inductor current information to obtain stabile current mode operation. the output voltage is divided by the resistive voltage divider at the fb pin. the internal transconductance error amplifier then amplifies the difference between the voltages at fb with the reference voltage. the error signal voltage is an input to the comp and is compared against the current signal which consists of both the inductor current and slope comp ramp at the pwm comparator input. if this current signal is less than the error voltage the high side switch will turn on. switching frequency the AOZ1253 has a fixed switching frequency under pwm mode of operation through an internal oscillator. its nominal switching frequency is set to 600khz.
AOZ1253 page 7 of 7 rev. 1.1 march 2012 www.aosmd.com output voltage setting the output voltage is set by a resistor divider network of r 1 and r 2 , by feeding back the output to the fb pin. the output setting is defined by: ? ? ? ? ? ? ? ? ? ? ? 2 1 1 6 . 0 r r v o below table 1 lists popular regulated outputs and the corresponding values of r 1 , r 2 . v o (v) r 1 (k ? ) r 2 (k ? ) 0.6 open 1.0 6.67 10 1.5 15 10 1.8 20 10 2.5 31.7 10 3.3 45 10 5.0 73.3 10 table 1.output voltage setting with resistor divider the combination of r 1 and r 2 should be large enough to avoid drawing excessive current from the output that contributes to power loss. since the switch duty cycle can be as high as 100%, the maximum output voltage can be set as high as the input voltage minus the voltage drop of the high side nmos and inductor . over current protection (ocp) the primary signal used in over current protection is the peak inductor. by employing pe ak current mode control, the comp voltage is proportional to the peak inductor current. this voltage falls between the range of 0.4v and 2.5v, increasing with output load current. AOZ1253 utilizes cycle by cycle current limit and limits the peak inductor current. a preset current limit voltage is used as a reference trip point. when the output current exceeds the current limit range, the high side switch will stop switching. under fault conditions where the output maybe shorted to ground, v out will drop rapidly and AOZ1253?s protection circuit will force the inductor current to decay once the ocp level is reached within several switching cycles. this feature helps to prevent catastrophic failure and recovery of the ic once the short is removed. AOZ1253 will initiate a soft start once the over-current condition is removed. thermal protection an internal temperature sensor monitors the junction temperature of the controller. the internal control circuit shuts down the high-side nmos once the junction temperature exceeds 150oc. the regulator has a 50 hysteresis and will automatically restart when the junction temperature decreases to 100oc. input capacitor the input bypass capacitor must be connected very closely to the v in and pgnd pins of AOZ1253. this mainly to ensure that proper filtering is maintained to filter out the pulsing input current inherent to buck regulator switching. the voltage rating of input capacitor is selected to be higher than maximum input voltage plus the input ripple voltage. the input ripple voltage can be approximated by equation below: in o in o in o in v v v v c f i v ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 since the input current is discontinuous in a buck converter, the current stress on the input capacitor is one key concern when selecting the capacitor. for a buck regulator, the rms value of input capacitor current can be calculated by: ? ? ? ? ? ? ? ? ? ? ? in o in o o rms cin v v v v i i 1 _ m equals the conversion ratio: m v v in o ? the relationship between the input capacitor rms current and voltage conversion ratio is calculated and shown in figure 1 below. it can be seen that when v o is half of v in , c in is under the worst current stress. the worst current stress on c in is 0.5i o . figure 1. i cin vs. voltage conversion ratio
AOZ1253 page 8 of 8 rev. 1.1 march 2012 www.aosmd.com to ensure reliable operation, the input capacitors must be selected to have a current rating higher than i cin-rms at the worst operating conditions. ceramic capacitors are preferred for input capacitors because of their low esr and high current rating. depending on the application circuits, other low esr tantalum capacitor may also be used. when selecting ceramic capacitors, x5r or x7r type dielectric ceramic capacitors should be used for their better temperature and voltage characteristics. note that t he ripple current rating from capacitor manufactures is based on certain amount of life time. further de-rating may be necessary in practical design. inductor the inductor is used to supply constant current to output when it is driven by a switching voltage. for given input and output voltage, inductance and switching frequency together decide the inductor ripple current, which is: ? ? ? ? ? ? ? ? ? ? ? ? ? in o o l v v l f v i 1 the peak inductor current is: 2 l o lpeak i i i ? ? ? high inductance gives low inductor ripple current but requires larger size inductor to avoid saturation. low ripple current reduces inductor core losses. it also reduces rms current through inductor and switches, which results in less conduction loss. usually, peak to peak ripple current on inductor is designed to be 20% to 30% of output current. when selecting the inductor, make sure it is able to handle the peak current without saturation even at the highest operating temperature. the inductor takes the highest current in a buck circuit. the conduction loss on inductor needs to be checked for thermal and efficiency requirements. surface mount inductors in different shape and styles are available from coilcraft, elytone and murata. shielded inductors are small and radiate less emi noise. but they cost more than unshielded inductors. the choice depends on emi requirement, price and size. output capacitor the output capacitor is selected based on the dc output voltage rating, output ripple voltage specification and ripple current rating. the selected output capacitor must have a higher rated voltage specification than the maximum desired output voltage including ripple. de- rating needs to be considered for long term reliability. output ripple voltage specification is another important factor for selecting the output capacitor. in a buck converter circuit, output ripple voltage is determined by inductor value, switching frequency, output capacitor value and esr. it can be calculated by the equation below: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? o co l o c f esr i v 8 1 where, c o is output capacitor value and esr co is the equivalent series resistor of output capacitor. when low esr ceramic capacitor is used as output capacitor, the impedance of the capacitor at the switching frequency dominates. output ripple is mainly caused by capacitor value and inductor ripple current. the output ripple voltage calculation can be simplified to: o l o c f i v ? ? ? ? ? ? 8 1 if the impedance of esr at switching frequency dominates, the output ripple voltage is mainly decided by capacitor esr and inductor ripple current. the output ripple voltage calculation can be further simplified to: co l o esr i v ? ? ? ? for lower output ripple voltage across the entire operating temperature range, x5r or x7r dielectric type of ceramic, or other low esr tantalum are recommended to be used as output capacitors. in a buck converter, output capacitor current is continuous. the rms current of output capacitor is decided by the peak to peak inductor ripple current. it can be calculated by: 12 _ l rms co i i ? ? usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. when the buck inductor is selected to be very small and inductor ripple current is hi gh, output capacitor could be overstressed.
AOZ1253 page 9 of 9 rev. 1.1 march 2012 www.aosmd.com loop compensation the AOZ1253 employs peak current mode control for ease-of-use and fast transient response. peak current mode control eliminates the double pole effect of the output l&c filter. it greatly simplifies the compensation loop design. with peak current mode cont rol, the buck power stage can be simplified to be a one-pole and one-zero system in frequency domain. the pole is dominant pole can be calculated by: l o p r c f ? ? ? ? 2 1 1 the zero is an esr zero due to output capacitor and it?s esr. it is can be calculated by: co o z esr c f ? ? ? ? 2 1 1 where, c o is the output filter capacitor; r l is load resistor value; and esr co is the equivalent series resistance of output capacitor. the compensation design is actually to shape the converter control loop transfer function to get desired gain and phase. several different types of compensation network can be used for the AOZ1253. for most cases, a series capacitor and resistor network connected to the comp pin sets the pole-zero and is adequate for a stable high-bandwidth control loop. in the AOZ1253, fb pin and comp pin are the inverting input and the output of internal error amplifier. a series r and c compensation network connected to comp provides one pole and one zero. the pole is: vea c ea p g c g f ? ? ? ? 2 2 where, g ea is the error amplifier transconductance, which is 1000 10 -6 a/v; g vea is the error amplifier voltage gain, which is 500 v/v; and c c is compensation capacitor in the typical application schematic on the first page. the zero given by the external compensation network, capacitor c c and resistor r c is located at: c c z r c f ? ? ? ? 2 1 2 to design the compensation circuit, a target crossover frequency f c for close loop must be selected. the system crossover frequency is where control loop has unity gain. the crossover is the also called the converter bandwidth. generally a higher bandwidth means faster response to load transient. however, the bandwidth should not be too high because of system stability concern. when designing the compensation loop, converter stability under all line and load condition must be considered. usually, it is recommended to set the bandwidth to be equal or less than 1/10 of switching frequency. it is recommended to choose a crossover frequency equal or less than 60khz. the strategy for choosing r c and c c is to set the cross over frequency with r c and set the compensator zero with c c . using selected crossover frequency, f c , to calculate r c : cs ea o fb o c c g g c v v f r ? ? ? ? ? ? 2 where, f c is desired crossover frequency. for best performance, f c is set to be about 1/10 of switching frequency; v fb is 0.6v; g ea is the error amplifier transconductance, which is 1000 10 -6 a/v; and g cs is the current sense circuit transconductance, which is 4 a/v. the compensation capacitor c c and resistor r c together make a zero. this zero is put somewhere close to the dominate pole f p1 but lower than 1/5 of selected crossover frequency. c c can is selected by: 1 2 5 . 1 p c c f r c ? ? ? ? equation above can also be simplified to: c l o c r r c c ? ?
AOZ1253 page 10 of 10 rev. 1.1 march 2012 www.aosmd.com pcb layout consideration as with all high current switching buck regulators, circuit board layout is the key in preventing inductive overshoots and undershoots transient spikes. there are essentially two high pulsing current loops in a synchronous buck converter. th e first switching loop is formed when the high-side mosfet is switched on. the circulating current flows from the input capacitors, to the filter inductor, to the output capacitors (load), then returns to the input capacitor through power ground. it is imperative that a low inductive ceramic capacitor be placed directly across vin (pin2) and pgnd (pin1) to reduce the switching loop during the high side turn on transition. the second loop is formed when the low-side mosfet is switched on during synchronous operation. this loop is formed from the inductor, to the output capacitors (load), then returns through the low-side mosfet. the pcb layout for the AOZ1253 is shown below. it can be seen that the input bypassing capacitors are placed in close proximity to vin and pgnd. analog ground and power grounds are separated to filter out noise from the main power switching loops. the sensitive nodes that require connection through analog ground (agnd) are comp, fb, and vss. pcb guideline that can be helpful: 1. the exposed (lx) node serves as the interconnect of both high-side and low-side mosfets. it is suggested that a large copper plane added underneath the ic to improve thermal dissipation. 2. to improve high-side thermal dissipation, maximize the copper area connected to the vin pin. 3. the input capacitor should be connected in close proximity to the vin pin and the pgnd pins. 4. a ground plane is strongly recommended. separate pgnd from agnd and connect them at a single point to avoid noise coupling. 5. form a short wide trace from lx to the output inductor and capacitors. 6. the lx switching node is the noisiest of all pins; therefore, all sensitive nod es must be far away from this pin.
AOZ1253 page 11 of 11 rev. 1.1 march 2012 www.aosmd.com package dimensions, exposed pad so-8
AOZ1253 page 12 of 12 rev. 1.1 march 2012 www.aosmd.com tape and reel dimensions, exposed pad so-8
AOZ1253 page 13 of 13 rev. 1.1 march 2012 www.aosmd.com part marking this datasheet contains preliminary data; suppl ementary data may be published at a later date. alpha and omega semiconductor reserves the right to make changes at any time without notice. life support policy alpha & omega semiconductor products are not author ized for use as critical components in life support devices or systems. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. a oz1253pi (epad so-8) z1253pi fa part number code assembly lot code year & week code lt yw fab & assembly location

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